1. Field of the Invention
The present invention relates generally to integrated circuit fabrication, and more particularly to processes for forming metal structures in integrated circuits.
2. Description of the Background Art
The speed at which a signal is propagated in an integrated circuit is limited by the delay through the interconnect line carrying the signal. This delay, commonly known as xe2x80x9cRC delay,xe2x80x9d is due to the resistance and capacitance of the interconnect line. Reducing the resistance or capacitance of an interconnect line lowers its RC delay and increases signal propagation speed. Thus, reducing the RC delay of interconnect lines plays a major role in making integrated circuits run faster.
Using a low-resistance interconnect material such as copper helps lower the resulting RC delay. To reduce capacitance, the thickness of the dielectric layer separating the interconnect line from the substrate may be increased. The just mentioned dielectric layer may be made of a low dielectric constant material, also referred to as a low-k dielectric, to further reduce capacitance on the interconnect line. For similar reason, low-k dielectrics may also be used between side-by-side or overlying interconnect lines.
A low-k dielectric is also desirable in forming an inductor in an integrated circuit. The quality factor (xe2x80x9cQxe2x80x9d) of such an on-chip inductor is affected by the capacitance between a metal portion of the inductor and an underlying substrate, and the capacitance between metal portions of the inductor. The use of low-k dielectrics lowers capacitance in the aforementioned inductor regions, and thereby increases the Q of the inductor.
A low-k dielectric region may be formed by using a TEOS oxide to fill gaps between metal lines. The inability of the TEOS oxide to completely fill the gaps results in air gaps between the metal lines. Because air has a dielectric constant of 1, the resulting air gaps help lower capacitance. However, the formation of the resulting air gaps is not controllable, and their size varies depending on the metal etch profile and available space. Additionally, the TEOS oxide fills the space between metal layers. Various relatively complicated unity-k dielectric structures have also been proposed to lower capacitance on metal lines.
The present invention relates to a novel method of forming a floating metal structure in an integrated circuit. In one embodiment, a dielectric region separates a floating metal structure from an underlying substrate or another floating metal structure. The dielectric region is an air core rather than a dielectric material. Because air has a dielectric constant of 1, the resulting dielectric region provides relatively low capacitance. The present invention may be used in a variety of applications including, without limitation, in the formation of interconnect lines and on-chip inductors.
In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.
These and other features and advantages of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.